The present invention relates to semiconductor manufacturing, and more specifically, to a method for manufacturing tunnel field effect transistor (FET) structures implementing a replacement spacer.
Power consumption of conventional microprocessors can be lowered by dropping supply voltage Vdd. Conventional metal oxide semiconductor FETs (MOSFETs) at lower Vdd have degraded Ion-Ioff performance. To maintain similar Ion-Ioff performance as today's state-of-the-art CMOS at low Vdd, devices with sub-threshold slope S<60 mV/decade are implemented. For achieving S<60 mV/decade, non-thermionic turn-off mechanisms, such as impact ionization or band-to-band tunneling, are implemented. Impact ionization requires very high voltages and generates hot carriers that lead to poor reliability when used in conjunction with a gate oxide for achieving gate-controlled impact ionization. Gate oxide degradation due to hot-electron effects is avoided in MOSFETs due to reliability concerns. Gate-controlled, source-side band-to-band tunneling can be utilized for achieving S<60 mV/decade. Tunnel FETs can, in principle, be operated at low Vdd. Furthermore, tunnel FETs are not expected to suffer from any known reliability issues.
Among tunnel FETs using Si/SiGe heterojunctions, known device structures include a p+ SiGe source, p-Si or i-Si body, and n+ Si drain for N-channel FETs, as shown below. The method for forming the structure leads to the gate oxide being exposed to epi preclean that is performed prior to source-side SiGe epitaxy. Epi preclean is done for preparing a clean surface for epitaxy and generally consists of a wet etch that includes HF for removing native oxide. This HF etch leads to local thinning of the exposed gate oxide and can completely remove the exposed gate oxide, thereby leading to gate-to-source shorts.